[libre-riscv-dev] Status on Our RISCV Implementation
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Mar 24 13:58:20 GMT 2020
On Tue, Mar 24, 2020 at 1:11 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:
> > nope. not for RISC-V. userspace only.
> So I guess we’d have a POWER kernel…
correct. and POWER TLBs and MMU.
> If a binary tries to call RISCV instructions to set supervisor mode register - how is that handled?
from userspace? fail... just like any other userspace RISC-V program
is not permitted to set a supervisor mode register on any standard
there will *be* no supervisor mode RISC-V... therefore implementation
of supervisor mode RISC-V registers is completely unnecessary.
userspace RISC-V is only permitted to set userspace RISC-V CSRs.
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