[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #100 from Jacob Lifshay <programmerjake at gmail.com> ---
one issue with qemu is that it doesn't properly implement everything -- for
example, it doesn't appear to implement the FPSCR.FR bit (I've been reading its
source as an additional reference for simple-soft-float).

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