[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Mar 24 08:50:51 GMT 2020


--- Comment #101 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #100)
> one issue with qemu is that it doesn't properly implement everything -- for
> example, it doesn't appear to implement the FPSCR.FR bit


> (I've been reading
> its source as an additional reference for simple-soft-float).

ok so when it comes to FP we can't expect that to work.  by then we should be a
long way forward at least with running something.

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