[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #99 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://access.redhat.com/documentation/en-us/red_hat_enterprise_linux/6/html/virtualization_administration_guide/sect-vish-dump

crashdump --memory only would get a .elf file with memory and registers.

executing a bare metal .bin file under qemu with a small memory would give
something not too massive to parse

https://github.com/eliben/pyelftools/blob/master/examples/dwarf_decode_address.py

hmm it seems there are at least 2 different python elf parsers.

the only thing we have to watch, these are big dependencies we're pulling in
(i'm on a mobile 4G connection). luckily i have qemu already installed

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