[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Mar 24 01:49:41 GMT 2020


--- Comment #99 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

crashdump --memory only would get a .elf file with memory and registers.

executing a bare metal .bin file under qemu with a small memory would give
something not too massive to parse


hmm it seems there are at least 2 different python elf parsers.

the only thing we have to watch, these are big dependencies we're pulling in
(i'm on a mobile 4G connection). luckily i have qemu already installed

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list