[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #98 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/simulator/test_sim.py;hb=HEAD

y'know... the comment "checked this against qemu" got me thinking. this looks
like it could be used to actually run any of:

* qemu
* the simulator
* the score6600 engine
* pearpc
* gem5

i know qemu can be run in bare metal mode, console only, for example.  it would
not be cycle accurate however would give us a jumpstart on running really basic
programs.

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