[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Mar 24 01:28:01 GMT 2020


--- Comment #98 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

y'know... the comment "checked this against qemu" got me thinking. this looks
like it could be used to actually run any of:

* qemu
* the simulator
* the score6600 engine
* pearpc
* gem5

i know qemu can be run in bare metal mode, console only, for example.  it would
not be cycle accurate however would give us a jumpstart on running really basic

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