[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=257

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> hmmm connected to LDSTCompAlu we need something that, after splitting the
> address and len into two, can "reconstruct" the LD/ST

this basically adds 16 to the real address and masks off the top bytes that
overrun a 16 byte cache line.

there needs to be two latches which are in "passthrough" mode (in case the twin
data is available immediately) and if one is not available, wait until it is
before responding "ok".

also needs to pass through exceptions back to the LDSTCompAlu

the interesting thing is, the interface is almost certainly identical to the
minerva LoadStoreInterface class.

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