[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=257

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hmmm connected to LDSTCompAlu we need something that, after splitting the
address and len into two, can "reconstruct" the LD/ST

i'm also going to suggest that we have a preanalysis phase on LD/STs for VL and
make it SIMD-like, up to 64 bit.

so if a VL=4 LD comes in on a halfword operation it is turned into a 64 bit
request.

the only thing to watch out for there is mem faults.  the last 16 bits failing
should *not* cause the other 3 16 bit LDs in that "batch" to fail.

we can incrementally add this as an optimisation, later

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