[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=257

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/scoreboard/addr_split.py;h=40f4569c38defa7fbf31b68f186f064d2df3e732;hb=f58721bc872b0e0b487a14dfa6a816774b433892

putting together a basic LD/ST address-splitter.  however it includes
signalling which will connect directly to CompLDST.

basically, the address+len expands to a bit-mask, that could be mis-aligned,
so the "normal" half is sent truncated on a cache-line-boundary and the "top"
half is split into a *second* LD/ST.

what that means is that the LDSTCompUnit now needs to wait for *TWO* LD/STs
to complete.

therefore, we need valid/data signalling for *two* LD/STs and, on successful
completion of *both*, the data needs "re-assembly" based on the *two* masks

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