[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Mar 21 00:48:09 GMT 2020


--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hang on a minute...

if we use a very small but wide L1 cache, with the following characteristics,
does it do the job?
* 8 sets
* 16 way set associative
* byte per way

the 16 bit mask *is* the 16 way selector

then i think, if you make a N-in/out multiplexor to write to each byte, the
job's done.


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