[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Mar 20 20:21:40 GMT 2020


--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

they set the cache up to be a maximum of 2-way.  however that's not the same as
the number of read/write ports.  arg.

ok i found a diagram which explains it:

it shouuuld be relatively straightforward to augment that to be dual-ported,
although let's not do that straight away.

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