[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=257

--- Comment #10 from Jacob Lifshay <programmerjake at gmail.com> ---
I've been thinking that we would have a cache with a cache line size of 64
bytes (or 32 if we really have to).

we want the cache line size to be the same for all our caches since it greatly
simplifies cache to cache transfers.

So, for a 32kB L1 cache, it would have 512 lines. If we had it be 8-way set
associative, then there would be 64 sets and each set would have 8 lines.

Having a L1 cache much smaller than 16kB would be quite detrimental due to the
excessive cache latency and lack of bandwidth to the L2.

I'm going to be unavailable till at least Sat night, then will work on
publishing v0.2 of algebraics (updating transitive dependencies for
simple-soft-float due to PyO3 v0.9 being released) then work on this.

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