[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #89 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok i fixed some dumb off-by-one errors in decode_fieldsn.py and the gas example
works (yay!)  am tempted to suggest throwing a ton more random stuff at it.

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