[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #88 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
michael, fired up laptop brielfly when stopped git commited field-index reverse
please check it, should work.

-- 
You are receiving this mail because:
You are on the CC list for the bug.