[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Mar 19 15:29:55 GMT 2020


--- Comment #90 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #89)
> ok i fixed some dumb off-by-one errors in decode_fieldsn.py and the gas
> example works (yay!)  am tempted to suggest throwing a ton more random stuff
> at it.

Yep, looks like you fixed the register thing. 
I'll get to adding more instructions later today

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list