[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #77 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #76)
> From what I understand, it's just the way bits are numbered that's reversed,
> the MSB is still the MSB. So, just the field order is reversed, individual
> fields are not since they are treated as a multi-bit number and the MSB is
> still the MSB (and other bits also keep their place in a number).

ngggh mindbender.  so by doing width-idx-1 it has reversed the bitorder of each
bit in the field.

ye gods.

can you and michael take a look at this properly, suggest reviewing the pearpc
and gem5 source code, and chiselwatt.

-- 
You are receiving this mail because:
You are on the CC list for the bug.