[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #78 from Jacob Lifshay <programmerjake at gmail.com> ---
In any case, what matters is that the instructions are decoded correctly.

Some example disassembly from objdump (edited to convert decimal to hex):

test.o:     file format elf64-powerpcle


Disassembly of section .text:

0000000000000000 <f>:
   0:   01 00 20 3d     addis   r9,0,1
   4:   45 23 29 61     ori     r9,r9,0x2345
   8:   d2 49 84 7c     mulld   r4,r4,r9
   c:   d2 19 64 7c     mulld   r3,r4,r3
  10:   20 00 80 4e     bclr    20,lt

Note how the immediate values for ori and addis are not bit-reversed (they are
in little-endian byte order, though). I haven't checked, but I'm quite sure the
register fields are also not bit-reversed.

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