[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Immanuel, Yehowshua U
yimmanuel3 at gatech.edu
Wed Mar 18 18:23:46 GMT 2020
> howevrr i dont know what "downto" means in vhdl.
VHDL: 8 downto 0
VHDL is really weird...
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