[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Mar 18 16:12:33 GMT 2020


--- Comment #75 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #74)
> (In reply to Michael Nolan from comment #73)
> > Huh, apparently the register numbers need to be bit reversed in our decoder.
> eeeverything needs to be bit-reversed. see 1.3.2 "notation"

Well yes... But I thought we did that already, evidently not. 

> if you can double-check that, it would be really good.  i tend
> to get these things wrong.


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