[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #76 from Jacob Lifshay <programmerjake at gmail.com> ---
>From what I understand, it's just the way bits are numbered that's reversed,
the MSB is still the MSB. So, just the field order is reversed, individual
fields are not since they are treated as a multi-bit number and the MSB is
still the MSB (and other bits also keep their place in a number).

Example:
Power bit order:
bit # 0 1 2 3 4 5 6 7
      0 1 0 1 1 1 1 0

fields: A:0-3, B:4, C:5-7

field A 0-3: 0101 = 5
field B 4: 1 = 1
field C 5-7: 110 = 6

switched bit numbering order:

nmigen/RISC-V bit order:
bit # 7 6 5 4 3 2 1 0
      0 1 0 1 1 1 1 0

fields: C:0-2, B:3, A:4-7

fields have same value but different order:
field C 0-2: 110 = 6
field B 3: 1 = 1
field A 4-7: 0101 = 5

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