[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #74 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #73)
> Huh, apparently the register numbers need to be bit reversed in our decoder.

eeeverything needs to be bit-reversed. see 1.3.2 "notation"

- Bits in instructions, fields, and bit strings are
  numbered from left to right, starting with bit 0
- The leftmost bit of a sequence of bits is the
  most significant bit of the sequence.

*gibber*.

so i put the reversing into.. err... where was it...
SignalBitRange.__getitem__() - you can see (i just commented it)

if you can double-check that, it would be really good.  i tend
to get these things wrong.

ultimately, we'll find out pretty damn quick when it comes to
executing actual code.

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