[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Mar 18 15:49:56 GMT 2020


--- Comment #73 from Michael Nolan <mtnolan2640 at gmail.com> ---
Huh, apparently the register numbers need to be bit reversed in our decoder.

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