[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #73 from Michael Nolan <mtnolan2640 at gmail.com> ---
Huh, apparently the register numbers need to be bit reversed in our decoder.

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