[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

[Jacob Lifshay]

On Sun, Mar 15, 2020, 15:04 Staf Verhaegen <staf at fibraservi.eu> wrote:

> Immanuel, Yehowshua U schreef op zo 15-03-2020 om 19:52 [+0000]:
> > >
> > > Later (for Libre-SOC v2 or v3), it might be a good idea to add support
> for
> > > x86 and x86_64 user-mode since the patents for the base ISA will have
> > > expired by then. This would help give us an advantage since it would
> allow
> > > us to run legacy software.
> >
> >
> > Isn’t x86 kinda big - like a 1000+ instructions? How would this impact
> our power target…
> >
> > But other than that, I’m all for adding x86 support.
>
> If you consider implementing x86 instruction set you also need to
> consider the risk of patent lawsuits being filed at you...
>

that's true, but if you only implement the parts where all the patents have
expired, then they'll have a hard time suing you for patent infringement.

Jacob