[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

[Luke Kenneth Casson Leighton]

On Sun, Mar 15, 2020 at 8:00 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:
>
> > x86 and x86_64 user-mode since the patents for the base ISA will have
> > expired by then
>
> Did you hear THAT intel?

haha :)