[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Sun Mar 15 20:00:02 GMT 2020

> x86 and x86_64 user-mode since the patents for the base ISA will have
> expired by then

Did you hear THAT intel?
Soto voice: Watch out

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