[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Sun Mar 15 19:52:44 GMT 2020

> Later (for Libre-SOC v2 or v3), it might be a good idea to add support for
> x86 and x86_64 user-mode since the patents for the base ISA will have
> expired by then. This would help give us an advantage since it would allow
> us to run legacy software.

Isn’t x86 kinda big - like a 1000+ instructions? How would this impact our power target…

But other than that, I’m all for adding x86 support.

But yeah, the main thought in my head for sticking with a single ISA is power consumption.

Also, we should develop our codebase such that we can easily generate RTL that can target RISCV or POWER…

Like ``python3 builds.py —target RISCV64`` for example.

In other words, we should be able to parametrize by architecture:
or perhaps:

``python3 builds.py —target RISCV64+POWER``

This seems like a good feature and will probably encourage sustainable programming practices.


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