[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U
yimmanuel3 at gatech.edu
Sun Mar 15 19:37:07 GMT 2020
> i've added this source code - wholesale - into the soc repo:
Note, I’ve spoken to Jean Francois Nguyen, the developer of Minerva.
He said that he can’t guarantee the pipeline dependencies are correctly implmented and
has done little to no formal verification on Minerva.
He said Minerva was just more of a proof of concept for nMigen.
So please keep that in mind.
@Luke, what did you want to use Minerva for?
On the other hand, VexRISCV is pretty well tested - although its in Chisel…
Maybe someone would care to translate it to nMigen.
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