[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Mar 15 19:07:09 GMT 2020

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sun, Mar 15, 2020 at 6:20 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:
> > massively - and provided us with a way to test it, so that when it
> > comes to implementing it in hardware, the *hardware* can be verified
> > immediately.
> So it sounds like the only benefit of RISCV was the RISCV spike emulator which allowed us to test our SimpleV proposal.

it was much more than that: the formal testing, the emulation, the
bootloading, the buildroot - replicating all of these is almost a
YEAR's work.

we're doing silicon *in october*... with *no working powerpc software
simulator* let alone working hardware.

again, to emphasise: we *need* to do an "incremental approach".  not
having the pieces of the puzzle to be able to leapfrog from stone to
stone in small increments means that we are dead in the water until
those pieces are in place.

> I’m still not clear how keeping RISCV compatibility helps us?

we made a promise to our backers (including at least one sponsor who
is donating USD 500 a month).

> It seems to me like excuses to keep RISCV around than an actual need to continue with it.

on one hand we have financial backers on whom we depend.

on the other: if we bootstrap our way up the "ladder" by way of RISC-V
*FIRST*, we can "cross bootstrap" to POWER in SIDEWAYS small


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