[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

[Luke Kenneth Casson Leighton]

On Sun, Mar 15, 2020 at 7:33 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:
>
> OK.
>
> So to sum up - we have limited funding currently, and we want to have
> something to show hopefully by October -

we're *going* to meet the tapeout deadline in October.  exactly what
with will be cut - in a draconian and clinical fashion - to *make*
that goal achievable.

> progress on RISCV is already well underway.

was.

*was* underway, until the RISC-V Foundation fucked us over, yes.


> Lets make this prominent on the website - that we’re currently doing Dual ISAs.
>
> Once we do get a lot of more funding, I would eventually like to move to only supporting one architecture which seems to be POWER right now. I say this because I believe supporting DUAL ISA down the road will cause more headaches than its worth.

well, once it's done it's done.

> Not that it isn’t possible, but its notably non-trivial and adds little value to most customers.

honestly i think you're right.  if we were doing ARM or x86 Dual ISA,
i'd say it had "real value".

> We can explain this to our backers - people can be flexible - especially over a cup of tea.
>
> However for right now, the risk minimizing move (if I understand everything correctly) is to maintain the position of supporting both ISA with incremental additions of POWER.

basically, so as not to be critically dependent on investment.

one of the biggest mistakes that any entrepreneurial team can make is
to make plans that ASSUME - as a critical dependency - the "existence
of VC funding".


> Who knows, I could be wrong. Maybe people really would find a use for dual ISAs - but up front, to investor for example, and to me, it looks unnecessary.

if an investor drop USD $10m onto the project, tomorrow, RISC-V goes.

if they *don't*, then we carry on with the plan that we have, and that
*most likely* means an incremental bootstrap process by way of RV32
(Minerva), RV64, RV64GC *and then* POWER *and then* SimpleV

why?

each of those is a *SMALL* incremental step.

l.