[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Mar 15 19:25:57 GMT 2020

On Sun, Mar 15, 2020 at 7:24 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Sun, Mar 15, 2020 at 7:20 PM Immanuel, Yehowshua U
> <yimmanuel3 at gatech.edu> wrote:
> >
> > Or, is the internal format some sort of intermediate that both RISCV and POWER instructions map down to?
> yeees.

now you've got it.

and that internal format is trivial.  single-bit wires.

to do a 32-bit to 32-bit translator is a MASSIVE piece of silicon that
has to preserve every nuance of the instructions...

oh... err... and once it's translated to POWER, it has to go through
*another* translation process, to be decoded into the internal format?

errr no.


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