[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

[Luke Kenneth Casson Leighton]

On Sun, Mar 15, 2020 at 7:17 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:

> > no it doesn't, at all.  here's the ISA tables:
> > https://libre-riscv.org/openpower/isatables/
>
> So RISCV is ONLY in software at this point - that is no RISCV on the actual hardware?

i've added this source code - wholesale - into the soc repo:
https://github.com/lambdaconcept/minerva

> And I know I seem a little pushy - but I have to be able to justify RISCV support upfront.
> To put it differently, if you can convince me of the value of retaining RISCV, then you can convince anyone.

i spent five months on adding SimpleV to spike.

*we do not have a working simulator for powerpc let alone have one
that has SV added to*

simple math.

estimated time to develop RISC-V SV hardware: about 4 man-months

estimate time to develop POWER SV hardware: at least ONE MAN-YEAR
because we DO NOT HAVE A SIMULATOR.

it's real simple.

if however we get USD $10m funding it's not an issue because we can
find a ton of people.

l.