[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Mar 15 11:20:16 GMT 2020

On Sun, Mar 15, 2020 at 7:19 AM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:

> > 1) where are the unit tests?
> > 2) where is the simulator?
> > 3) where is the port of softfloat-3 that supports POWER IEEE754 format?
> So what I’m hearing is that spike combined with risk-isa-tests has sped up the development process.

massively - and provided us with a way to test it, so that when it
comes to implementing it in hardware, the *hardware* can be verified

bear in mind that the full hardware will run (in nmigen simulation
form) at *seconds* per cycle.  compiling with iverilog will be better
but nothing like an FPGA.

each level of additional complexity and time for compilation means yet
more delay in finishing... and not having unit tests actually means
*we can't declare it finished*.

> Now, we just need a way to map POWER onto Simple-V?

not quite.

1) first we need a suitable POWER simulator.  it needs to be 64-bit,
LE and BE capable, with a full MMU, and capable of running bare-metal
tests as well as a full GNU/Linux 64-bit OS (even if that's in-memory,
like spike)
2) we then need a full set of bare-metal unit tests
3) *then* we add SImple-V to POWER at the *specification* level
4) *then* we implement Simple-V in the POWER simulator
5) *then* we implement bare metal unit tests capable of running in the
POWER simulator
6) *then* we implement POWER in hardware
7) *then* we run the unit tests from step 2 under the hardware
8) *then* we add SimpleV to POWER in hardware
9) *then* we run the unit tests from step 5 under the hardware

it's a hell of a lot of work - a lot more than with RISC-V.  with
RISC-V the fact that spike and the unit tests exist *and work* is a
massive, massive head-start, where not only do we not have to do the
research to get that working, we can use it by examining even the
source code of the simulator to actually see what's going on [spike
actually implements RISC-V UNIX Platform TLBs, and throws full and
correct page-fault exceptions].

> How does the decoder Michael is working on fit in?

it's a decoder.  if you don't have it, you can't decode POWER
instructions.  it's an essential part.


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