[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

[Immanuel, Yehowshua U]

> * take spike, and add SimpleV (done - took 2-3 months appx)
> * take riscv-isa-tests, and add SimpleV unit tests (done - took about 1 month)
> * implement a core in hardware by taking an existing core and adding
> in our engine.
> * run the EXACT SAME BARE METAL UNIT TESTS.
> 
> hardware is bootstrapped.  it's done in an incremental fashion, *one*
> unknown at a time.
> 
> now let's look at POWER.
> 
> 1) where are the unit tests?
> 2) where is the simulator?
> 3) where is the port of softfloat-3 that supports POWER IEEE754 format?

So what I’m hearing is that spike combined with risk-isa-tests has sped up the development process.

Now, we just need a way to map POWER onto Simple-V?
How does the decoded Michael is working on fit in?

Yehowshua