[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U
yimmanuel3 at gatech.edu
Sun Mar 15 07:18:54 GMT 2020
> * take spike, and add SimpleV (done - took 2-3 months appx)
> * take riscv-isa-tests, and add SimpleV unit tests (done - took about 1 month)
> * implement a core in hardware by taking an existing core and adding
> in our engine.
> * run the EXACT SAME BARE METAL UNIT TESTS.
> hardware is bootstrapped. it's done in an incremental fashion, *one*
> unknown at a time.
> now let's look at POWER.
> 1) where are the unit tests?
> 2) where is the simulator?
> 3) where is the port of softfloat-3 that supports POWER IEEE754 format?
So what I’m hearing is that spike combined with risk-isa-tests has sped up the development process.
Now, we just need a way to map POWER onto Simple-V?
How does the decoded Michael is working on fit in?
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