[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Sun Mar 15 18:19:54 GMT 2020

> massively - and provided us with a way to test it, so that when it
> comes to implementing it in hardware, the *hardware* can be verified
> immediately.

So it sounds like the only benefit of RISCV was the RISCV spike emulator which allowed us to test our SimpleV proposal.

I’m still not clear how keeping RISCV compatibility helps us?

It seems to me like excuses to keep RISCV around than an actual need to continue with it.


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