[libre-riscv-dev] next tasks

[Hendrik Boom]

On Thu, Feb 20, 2020 at 09:39:21AM +0200, Lauri Kasanen wrote:
> On Wed, 19 Feb 2020 14:14:16 +0000
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> 
> > we only have a few months in which to hang together all of the pieces
> > that have been put together, to make a 64-bit 180nm chip.  because
> > we're not doing this in verilog i believe it is reasonably doable, if
> > we take steps to cut "unnecessary" things out i.e. not do too much.
> > chop out L2 cache for example.
> 
> What about the C/C++ simulator/interpreter timeline? It's not a blocker
> for the hw tapeout, but it is a blocker for my work, which probably
> mostly won't make it for the simple Oct tapeout anyway.

What is it you want with this?  An implementation of C/C++ for the new SoC?
Or a simulation of the new SoC instruction set in C/C++?  Would it be good 
enough to have a simulator of the new SoC in any widely available programming 
language?

-- hendrik
> 
> - Lauri
> 
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev