[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sun Mar 8 15:31:26 GMT 2020


--- Comment #70 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

ok made a start on the register / immediate / spr / etc. decoder.  it will
need careful double-checking (help appreciated) not just against anton's
original work (decode2.vhdl and other files), against the PDF V3.0B manual
as well.

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