[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #70 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/decoder/power_decoder2.py;h=34ac66836870324a55840d890ffc741a98845fb5;hb=HEAD

ok made a start on the register / immediate / spr / etc. decoder.  it will
need careful double-checking (help appreciated) not just against anton's
original work (decode2.vhdl and other files), against the PDF V3.0B manual
as well.

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