[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #69 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok i now have the other section of the specification decoded (1.7 Instruction
Fields in 3.0B, 1.6.8 Instruction Fields in 2.07B)

this basically will allow us to construct python objects that, when used, will
allow the following:

FormX.FRSp[0:-1]

this will return bits 6 thru 10 of the instruction (*sigh* actually bits 31-6
thru 31-10) because all the indices are appropriately recorded in memory.

this even works on multi-bit fields such as this:

dc,dm,dx (25,29,11:15)
    Immediate fields that a
    Data Class Mask.
    Formats: XX2

which would be accessed as:

FormXX2.dc_dm_dx[0:7] where 

FormXX2.dc_dm_dx[0] would return bit 25 (okok 31-25)
FormXX2.dc_dm_dx[1] would return bit 29 (okok 31-29)

and so on.

it's still a bit of work to do.

i think this will be a heck of a lot easier than messing about trying to
memorise bit-field numbering, constantly having to refer back to the PDF spec.

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