[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #71 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/decoder/power_decoder2.py;h=5d706d9386e2f65e666d4a06408d43c1547c3913;hb=HEAD#l315

pulling it all together, some pieces still missing, needs a bit of rework:
classes that return "register num plus register valid" as an object, that
sort of thing, otherwise there's a lot of things to copy, laboriously.

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