[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #62 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #61)
> We should check the spec to see what its conventions are -- some use bit 0
> as MSB, some as LSB. Also, the memory interface may or may not byte swap.

i *think* it's a combination of these two things, from V2.07B, P35, section
1.3.2 "Notation":

- Bits in instructions, fields, and bit strings are
  numbered from left to right, starting with bit 0

- The leftmost bit of a sequence of bits is the
  most significant bit of the sequence.

which is about as obtuse and technically correct as it's possible to get.
having *separate* numbering for the ordering of the bits then specifying
that the bits are ordered in MSB??

wtf?? :)

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