[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Mar 5 15:46:33 GMT 2020


--- Comment #61 from Jacob Lifshay <programmerjake at gmail.com> ---
We should check the spec to see what its conventions are -- some use bit 0 as
MSB, some as LSB. Also, the memory interface may or may not byte swap.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list