[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #60 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #59)

> > page 15 of Power V2.07B
> > 
> > 0      6    11    16     21    31
> >   OPCD   RT    RA    ///    XO   /
> >   OPCD   RT    RA    RB     XO   /
> 
> Right, endianness. Ugh.

ah, maaan - it's byte-endian, isn't it?  so it's not quite as straightforward
as bit-reversal.  *sigh*.

i'm tempted to suggest complying with what's in the spec rather than
following exactly what anton did - then again that implies a lot of
work.

or having a close comparative look at chiselwatt.

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