[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #59 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #58)
> nngggh mmoooooo wtf why is the Power manual saying major opcodes are in bits
> 0-5 however microwatt and chiselwatt all specify the fields in *reverse*
> order??
> moooo?
> https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl
> majorop := unsigned(f_in.insn(31 downto 26));
> 
> page 15 of Power V2.07B
> 
> 0      6    11    16     21    31
>   OPCD   RT    RA    ///    XO   /
>   OPCD   RT    RA    RB     XO   /

Right, endianness. Ugh.

-- 
You are receiving this mail because:
You are on the CC list for the bug.