[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #153 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #150)

On my little Dell XPS 13 9370, it takes 3 minutes (and 6 seconds, ok)
for the whole P&R. I commited changes so it successfully complete.

To use the nsxlib standard cell libraries you must use the nsxlib
"DESIGN_KIT" in the Makefile. It needs 15.4% of free space, with
the "bloat profile" nsxlib (see coriolis2/settings.py).
The size seems twice bigger (in lambda) because the lambda in
sxlib is half the one of sxlib (for better technology fitting).

I also did make a print of it, but it is more than 1Mb so I will
directly email it to you.

You where getting VST errors in LVX most likely because the router
did not complete. You must look at:

  o  Computing statistics.
     - Processeds Events Total ..........................................
252198
     - Unique Events Total ..............................................
139250
     - # of GCells .......................................................
15376
     - Track Segment Completion Ratio .......................... 100%
[139250+0]
     - Wire Length Completion Ratio .......................... 100%
[13200080+0]
     - Wire Length Expand Ratio ......................... 4.64%
[min:12614970.5]
     - Unrouted horizontals .......................................... -nan%
[0]
     - Unrouted verticals ............................................ -nan%
[0]
     - Done in ................................................. 22.48s,
105.5Mb
     - Raw measurements ............................ 22.4796s,
+108008Kb/856.2Mb

The completion rates must be 100% and you must have "+0" and no unplaced
segments
list afterwards.

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