[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #152 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #151)
> (In reply to Luke Kenneth Casson Leighton from comment #148)
> > (In reply to Jean-Paul.Chaput from comment #147)
> > > (In reply to Luke Kenneth Casson Leighton from comment #146)
> > > 
> > > > but, for now, success!  it's a mess, but it works.
> 
> I should now have made the relevant corrections.

ah! great! so i looked at doAlu16.py and it works as intuitively expected:
place the larger blocks, then call Etesian.place() and that just places the
*remaining* cells.

> I put under alliance-check-toolkit/benchs/nmigen/ALU16 a
> corrected version of your script. To run it graphically:
> 
>    $ make vst
>    $ make cgt
> 
>    Then Tools -> Python Scripts -> doAlu16
>    (or [SHIFT+P] [SHIFT+S])
> 
>    Then enjoy!

i can confirm it works.

i saw you put "BLOCKAGE1/2/3" in, i will look at that later.

> 
> The result is extremely messy, as the connectors of the blocks
> are very badly placed regarding each others.

yes, i had not got to the point of considering where best to put those.

now i can experiment with that.

> If you run multiple timmes (without make clean; make vst) you
> will get slightly different result as the alu16.vst is rewritten
> with the order of it's instances/signals changeds).

interesting.

> 
> Didn't answer earlier as my brain is mono-thread, so I process
> one task at a time only. 

sorry!  i did transfer to other things.

> Now catching up with the others questions...

ok.

would it help if i reported bugs on gitlab.lip6.fr? (i would need an account to
do so)

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