[libre-riscv-dev] Why nMigen?
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Mar 2 20:21:29 GMT 2020
On Mon, Mar 2, 2020 at 8:05 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:
> I love nMigen, but newcomers will probably be curious about why we use nMigen.
> Do we have a page explaining why?
jacob and i went through this very early on the list.
> Also check out the excerpt pasted at the end from here: https://danluu.com/why-hardware-development-is-hard/
> nMigen only emits synthesizeable Verilog by going through the Yosys AST engine.
that's factually incorrect / misleading. nmigen does not output
verilog *at all*. it *only* outputs yosys ILANG. anything that yosys
does is the responsibility of *yosys*, and that includes "outputting
we do not use verilog *at all*. the coriolis2 scripts go directly
from ILANG to BLIF, and from there coriolis2 goes through a subset of
VHDL (sufficient to express cells and the connections between them),
then turns that into layout locations plus routes, and that can then
be turned into a GDS file and even simulated (at the gate level).
Bluespec "solved" the problem by being written in Haskell, and thus
having both formal proofs and strict data type checking. it is
therefore one *HUNDRED* percent guaranteed that if the program
compiles - and it is compiled, not interpreted - it is also
ultimately though you just have to know what you're doing.
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