[libre-riscv-dev] Why nMigen?

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Mon Mar 2 20:25:53 GMT 2020

that's factually incorrect / misleading.  nmigen does not output
verilog *at all*.  it *only* outputs yosys ILANG.  anything that yosys
does is the responsibility of *yosys*, and that includes "outputting

That’s correct - I mean that nMigen ultimately gets translated to valid Verilog.

More information about the libre-riscv-dev mailing list