[libre-riscv-dev] Why nMigen?

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Mon Mar 2 20:05:45 GMT 2020

I love nMigen, but newcomers will probably be curious about why we use nMigen.

Do we have a page explaining why?

Also check out the excerpt pasted at the end from here: https://danluu.com/why-hardware-development-is-hard/

nMigen only emits synthesizeable Verilog by going through the Yosys AST engine.
So invalid nMigen and by extension invalid Verilog IS a syntax error.

Contrast this with Migen which just used scripts to flatten internal Migen DSL into an AST which then became Verilog.

Verilog does none of these things. To write Verilog that will produce correct hardware, you have to first picture the hardware you want to produce. Then, you have to figure out how to describe that in this weird C-like simulation language. That will then get synthesized into something like what you were imaging in the first step.

As a software engineer, how would you feel if 99% of valid Java code ended up being translated to something that produced random results, even though tests pass on the untranslated Java code? And, by the way, to run tests on the translated Java code you have to go through a multi-day long compilation process, after which your tests will run 200 million times slower than code runs in production. If you're thinking of testing on some sandboxed production machines, sure, go ahead, but it costs 8 figures to push something to any number of your production machines, and it takes 3 months. But, don't worry, you can run the untranslated code only 2 million times slower than in production 1. People used to statically typed languages often complain that you get run-time errors about things that would be trivial to statically check in a language with stronger types. We hardware folks are so used to the vast majority of legal Verilog constructs producing unsynthesizable garbage that we don't find it the least bit surprising that you not only do you not get compile-time errors, you don't even get run-time errors, from writing naive Verilog code.

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