[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=155

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> That really depends on the specifications and on the needs… 
> Indeed an all-digital PLL may be quite compact if the output 
> frequency running range is not too large. Analog PLL needs RC
> filters and it may be quite area hungry. 

i do not know what may be best, here.  honestly if we can get away
with multiplying up from 12 or 24 mhz, in reasonable easy
multiples up to 192mhz (let us assume that is a maximum for 350nm?)

then some digital counters can generate 1/3 of that, 1/4 of that,
1/5 of that, 1/90th, 1/29323th of that and so on.

in this way we can calculate, if we need 115200 baud for a UART,
then it can take the standard (non PLL) frequency 25mhz and just
divide/count.  this will be a straight digital circuit, clearly.

later, when we are not in 350nm, we need to be able to do USB2: this
is very specifically 480mhz (multiple of 24mhz).

some peripherals, such as RGMII... no, i am just checking a datasheet
for the RTL8211, the *PHY* generates the 125mhz input clock, and the
recipient SoC can then use *that*.  so that one is okay.

SDMMC i believe you have to generate a 48mhz clock.
https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c#L48

yes, so we need to be able to generate 48 mhz, and to then route that
out.

however for later SoCs, when we get to 40nm, 28nm, 22nm and so on, we will
need around 400mhz, 800mhz, 1200mhz possibly as high as 1.6ghz

the exact frequency is not hugely relevant, but given that this is intended
as a low-power SoC, being able to set good granularity (approximately
100mhz increments) is reasonably important.

but, going *very* specific - 192.9323 mhz, 28.239929292999 mhz, that is
not a priority at all.

* Quartz XTAL either 12.5mhz or 24mz internal clock.
* 2x, 4x, 8x, 16x internal 12.5/24mhz internal clock
* UART (4800 baud to 115200 baud or 2x or 4x that)
* SD/MMC up to 48mhz
* eMMC up to 100mhz 
* SPI 24mhz maximum
* HyperRAM 100mhz, 150mhz, 160mhz (if doing DDR, so internally 320mhz)
* I2C needs between 100 Khz and 0.4 Mhz.

so the slower ones (UART, I2C) can be done as a simple digital
counter / divider circuit.

the faster ones (HyperRAM, eMMC, main CPU clock) could be done with a
digital PLL that multiples 2/4/8/16, then perhaps a very *very* simple
divider/counter ( 1/3, 1/5, 1/6, 1/7 ) to minimise gate delay?

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