[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sun Mar 1 12:04:53 GMT 2020


--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dimitri Galayko from comment #7)
> Hello Libre-SOC team 
> thank you Jean-Paul for introducing me to this exciting community. 
> I would be happy to contribute with my experience in PLL design. 
> I need first to well understand the need. 

fantastic.  yes.

> >for a SoC, a programmable PLL is needed that set the clock rate at a
> >range of frequencies.  also, several clocks are needed for different
> >peripherals (such as SD/MMC needs 50mhz, UART needs variable rates
> >from 9600 to 115200 and above etc.)
> That is OK, this is a quite regular need for SOCs. Do you need several
> clocks signals at different frequencies running in parallel or a single
> signal but with programmable frequency? 

i believe by "parallel" you mean "in phase"?  i.e. that a single PLL
would generate (simultaneously) N, 2N, 4N and so on, all in lock-step?
i cannot think of a scenario where we would need this...

...the only exception being for DDR (double-data-rate), and that
we can generate with a single flip-flop.

i think we can get away with a single frequency from a single PLL,
where we will then, if we need multiple (non-phase-locked) frequencies
we simply lay out more than one block.

> A PLL is a block from a mixed electronics, especially if one needs frequency
> at the higher limit of the technology. At least the oscillator is designed
> according to a "custom" design flow, and other blocks may be digital or
> analog. 


> >* a way to cut that in coarse granularity (half, quarter, 1/8th, 1/16th)
> >* some digital counters (and dividers) that will cut it further 
> that is what is usually done
> >* some "register" control - Wishbone B4 for example - for setting parameters 
> I guess, this is required for programming the frequency? 

yes.  hunting around: there would be something like this:

which is then hooked in like this:

and, therefore, when the processor first boots up, the BOOT ROM's first
task will be to poke to a memory address representing the "slave" address
of the PLL register, setting it so that the PLL outputs a frequency of
say 25 mhz for the SD/MMC I/O interface.

at that point the BOOT ROM can start to actually *use* the SD/MMC interface!

before then, it would either be useless (non-functional) or run at only 8mhz

> >if a crystal is inconvenient (too analog) we can use a straight external
> >clock oscillator IC which generates 8mhz, 12.5mhz or other suitable stable
> >input frequency.
> What do you mean by « too analog » ? 


i mean, i know the voltage swing of 12.5mhz and 24/25 mhz crystals:
they're tiny (well below 0.1v if i remember correctly?).  i wasn't
sure if the designs that you are doing would need something more
along the lines of 1.8v, 3.3v or so.

if you _can_ do something that uses this type of XTAL that would be
fantastic, as they are very cheap, and a standard part:


these are around only USD $0.15 in china, so we greatly prefer these.
12.5mhz, 24 or 25mhz would be the typical crystal frequency.

> If a quartz oscillator is used, the
> reference clock generator itself may be implemented on chip (and it will be
> analog) or it is indeed possible to use some external devoted circuit which
> will generate a digital signal.

those 3225 XTALs are what, from a cost perspective for mass-produced SoCs
(which our project is), would normally be expected to be used, because they
are so low-cost.

i only mentioned the external IC because i have seen them used (once), and
it may be slightly easier:

however you can see from the increased cost, we would not be doing ourselves
a favour to require a $1 oscillator when the SoC is being designed to sell for
around $4!

therefore, the lower-cost quartz crystal, if you are able to do a circuit which
will use that as an external component, and to let us know what capacitance and
resistance is expected, that would be fantastic.

(as you know, Professor Galayko, i am however writing this for the benefit of
other readers), usually, the specification for the capacitance is very tight:
two capacitors between 3pF and 20pF are attached, to make sure that the
requirements of the ASIC circuit match, plus sometimes (not always) a 1Mohm (or
so) resistor in parallel can be required.

you can tell i have designed quite a few PCBs with SoCs, peripheral ICs and
Embedded Controllers :)

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