[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sun Mar 1 11:22:04 GMT 2020


Dimitri Galayko <dimitri.galayko at lip6.fr> changed:

           What    |Removed                     |Added
                 CC|                            |dimitri.galayko at lip6.fr

--- Comment #7 from Dimitri Galayko <dimitri.galayko at lip6.fr> ---
Hello Libre-SOC team 

thank you Jean-Paul for introducing me to this exciting community. 
I would be happy to contribute with my experience in PLL design. 
I need first to well understand the need. 

>for a SoC, a programmable PLL is needed that set the clock rate at a
>range of frequencies.  also, several clocks are needed for different
>peripherals (such as SD/MMC needs 50mhz, UART needs variable rates
>from 9600 to 115200 and above etc.)

That is OK, this is a quite regular need for SOCs. Do you need several clocks
signals at different frequencies running in parallel or a single signal but
with programmable frequency? 

>therefore we need not just an analog PLL which can do different
>frequencies, based on a (fixed?) stable input clock (crystal,
>usually), we need:

>* the actual PLL, to operate at a maximum frequency of the silicon
A PLL is a block from a mixed electronics, especially if one needs frequency at
the higher limit of the technology. At least the oscillator is designed
according to a "custom" design flow, and other blocks may be digital or analog. 

>* a way to cut that in coarse granularity (half, quarter, 1/8th, 1/16th)
>* some digital counters (and dividers) that will cut it further 
that is what is usually done

>* some "register" control - Wishbone B4 for example - for setting parameters 
I guess, this is required for programming the frequency? 

>if a crystal is inconvenient (too analog) we can use a straight external
>clock oscillator IC which generates 8mhz, 12.5mhz or other suitable stable
>input frequency.

What do you mean by « too analog » ? If a quartz oscillator is used, the
reference clock generator itself may be implemented on chip (and it will be
analog) or it is indeed possible to use some external devoted circuit which
will generate a digital signal.

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