[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sun Mar 1 12:41:56 GMT 2020


--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
oh, also SDRAM.  100mhz and 133mhz.  133mhz is 400/3, which can be achieved
(approximately) by 24mhz times 16 in the PLL, then a simple counter-divider
divide by 3.


this is the kind of simplistic flexibility we need, all based around doubling
quadrupling etc. a 12.5 or 24 mhz XTAL, rather than very specific targetted
analog frequencies.

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